Semiconductor Integrated Chips (ICs) are crucial elements of all electronic devices including computers and consumer electronics used in everyday lives, large servers and machines that control many parts of human lives everyday. For example ICs are used in critical defense machines, machine that control the flow of information, the Internet, other communication networks and various communication mechanisms, etc.
Almost 95% of the ICs produced modernly are manufactured using a well known Complementary Metal Oxide Semiconductor (CMOS) process technology. CMOS has been the most used process technology in ICs for the past half century and it is expected to be the technology of choice for many decades in future.
CMOS technology has made remarkable and significant progress in last couple of decades. As predicted by Gordon Moore in 1965 (known as Moore's Law), CMOS manufacturing technology has progressed to a new NODE every 2 years wherein CMOS transistor geometry is shrunk drastically such that a given IC is shrunk to almost half size in less than 2 years when re-designed and manufactured in next generation process. This improvement results in lowering the cost of manufacturing ICs and/or increasing the total amount of work that can be done by an IC.
In general, ICs manufactured using the newer technology are cheaper, more powerful and consume less energy. This trend has continued for many decades and is expected to continue for many years in future. An example of the improvement is that, not long ago, a supercomputer required a entire building of space, required a dedicated mini power plant to power and run air conditioner to cool all of the parts of the supercomputer and cost millions of dollars. Today, that same supercomputer fits in a small backpack sleeve and is powered by a small mobile battery. ICs have become so miniaturized in size, have low power requirements and very low costs that ICS are now used in inexpensive toys and provide very sophisticated control, monitoring, audio visual or robotics functions etc. Furthermore, current ICs are so reliable that they are integrated into critical devices such as pacemaker. They are so critical that entire country's defense infrastructure depends on them. The features, improvements and advantages of CMOS process technology has proven to be a gift to human kind and is expected to continue to be so for long time.
A CMOS device generally includes an N-type Metal Oxide Semiconductor (NMOS) transistor/device and/or a P-type Metal Oxide Semiconductor (PMOS) transistor/device (each of which is known as a MOS device or MOS transistor.) The NMOS and PMOS devices both work as voltage current switches or as voltage dependent current sources. When appropriate voltage is applied at a control node, the switch is ON and current flows between two terminals of the switch (the conducting switch) and when another voltage is applied at the control node the switch is OFF and no current flows between the two terminals of the switch (the non-conducting switch). Any MOS transistor has 4-terminals that include a “gate”, a “source”, a “drain” and a “body.”
Theoretically, for an NMOS device, a positive voltage on the gate terminal with respect to the voltage on the source terminal makes the NMOS act as an ON switch and the current flows from the source terminal to the drain terminal. Conversely, when voltage at the gate terminal is same as the voltage on the source terminal of the NMOS device, the NMOS device acts as an OFF switch and no current flows from the source terminal to the drain terminal or from drain terminal to the source terminal. Similarly, for a PMOS device, when a negative voltage is placed on the gate terminal with respect to the source terminal, the PMOS device acts as an ON switch the current flows from the source terminal to the drain terminal or from drain terminal to source terminal. Conversely, when the voltage on the gate terminal is equal to the voltage on the source terminal, the PMOS device acts as an OFF switch and no current flows from the source terminal to the drain terminal or from drain terminal to the source terminal. The “body” node in both NMOS and PMOS devices acts as a reservoir of mobile charges and helps these devices act as switches.
Modern NMOS and PMOS devices have some residual current between the source and the drain terminals even when the devices are supposedly OFF. There are other small currents in an actual MOS transistor that exist and are inherent in the NMOS and PMOS device designs and are known “flaws”. These currents are collectively called “leakage” current or “static” current. Leakage or static current is an unavoidable flaw in device behavior. Needless to say, in most cases, the leakage or static current is undesired and does not serve any meaningful purpose in an IC. Recently the leakage or static current has become significant percentage of the total current of the device.
With their switch like behaviors, CMOS transistors (NMOS and PMOS) are best suited for digital technology and more than 95% ICs in the world are designed using digital technology. In digital technology, all functions and computations are translated to only two states—“Zero”(0) and “One”(1), also called binary states. All logic functions, therefore, are constructed using binary states or binary logic. Logic gates that translate functions in binary logic are called Boolean functions or Boolean gates. These binary or Boolean gates are connected physically by wires to form a complete one-bit function or a multi-bit function. All computing functions are therefore converted to binary or Boolean functions using mathematics that follows Boolean algebra or binary algebra (algebra with base 2).
A Boolean gate or Boolean function is implemented using CMOS transistors that are connected to each other through conducting wires. Each CMOS transistor works as switch that behaves as a voltage controlled current source. There are two types of CMOS transistors including a PMOS type transistor and an NMOS transistor.
Even though energy consumption of electronic items (and hence ICs) has been decreasing drastically and continuously, recently there is increased emphasis on more power reduction in ICs because the total number of these ICs has been growing at very fast pace but more importantly because energy is fast becoming a costly and scarce resource globally. The Semiconductor industry has increased its efforts in reducing power consumption in ICs with renewed vigor and focus in last few years. Reduced power consumption will become an increasingly important design requirement of all ICs in future.
When logic functions are performed by ICs, currents flow from one node to another node which changes the voltage at each node thereby modulate the binary value of each node. In CMOS, any transition of a node consumes energy by conduction of current through an electric field. Thus, an IC consumes electrical energy to perform logic functions or for transporting a logic value from one to other place. This is called “dynamic” energy or “active” energy. Dynamic Energy or active energy consumed in unit time is called dynamic power or active power. A lot of research is being done in the semiconductor industry today to reduce active or dynamic power of ICs. Unfortunately, as mentioned earlier, practical CMOS devices and hence practical ICs also use “static” energy or “leakage” energy.
In recent years, the static energy/power used by an IC has become a significant portion of total power consumed by the IC. In some cases, the static power can be as much as almost half of the total power consumed by the IC. To make matters worse, while dynamic power can be reduced by reducing the activity of nodes through development of efficient computation algorithms, static or leakage power is hard to reduce and/or get rid of since the static or leakage power (from the static or leakage current) is inherent to the design of the MOS devices themselves.
Circuit designers connect NMOS and PMOS transistors to each other to form specific functions. Many basic Boolean gates are designed and implemented from a “library” of Boolean functions. FIG. 1 shows a general structure of a CMOS logic gate or CMOS logic function in existing CMOS Boolean technologies that includes a “pull up circuit” 101 and a “pull down circuit” 102 with each circuit made of MOS transistors connected together to perform part of the Boolean computation to provide the complete desired Boolean computation for the gate. These pull up and pull down circuits are connected to “Supply 1” 105 and “Supply 2” 106, respectively. Supply 1 and Supply 2 are the necessary voltage source and voltage sink nodes for currents to flow. “Supply1” 105 and “Supply2” also provide the voltage level references for logic “1” or Logic “high” and logic “0” or logic “low” for the functional gate, its internal nodes, input ports (103) and output ports (104).
Multiple CMOS Boolean gates can be connected together to form a more complex function with many inputs and many outputs. To connect one CMOS gate to another, the input of a “load” CMOS gate is connected to the output of “driver” CMOS gate. Many “inputs” of one or multiple loads can be connected to one output of a CMOS gate. Connection between CMOS gates depends on overall required logic function of the integrated CMOS gates. This general structure of a CMOS Boolean gate and CMOS Boolean function has been in existence and use for many decades in semiconductor designs. As described above, modern CMOS technology has an undesired component “the leakage current” that consumes power in any IC all the time unless special methods and structures are adopted to reduce or eliminate this current component.
It is important to examine general behavior of all computation nodes in an IC as a whole to understand and tackle the issue of leakage power or static power in all modern ICs and in particular ICs designed and manufactured using CMOS ICs since almost all ICs in modern world are designed and manufactured using CMOS.
A typical electrical behavior of all computation nodes, in any CMOS IC, is shown in FIG. 2 that shows one or more nodes' (184) behavior of a functional block in active mode. It has been well established in industry statistically that at any given clock interval, only 5%-to-15% of nodes make transition from logic ZERO to ONE or from logic ONE to ZERO and rest of the nodes retain their old value and do not transition. Alternatively, if a computation node is looked at in the time domain (where time is measure in number of clock cycles), it would make a transition, on an average, only 5%-15% time (where time is measured by number of clock intervals). As shown in FIG. 2, Node 1, Node 2, . . . , to Node n (184) make transitions only once in many clock cycles, otherwise they retain their logic status clock-cycle over clock-cycle. Transitions represent functional activity in a CMOS IC. This means most node don't participate in computation activities for more than 15% of time.
Furthermore, as shown in FIG. 3, even within a given clock cycle, when a node transitions (202), the transitioning current occurs for a very small percentage of clock period (203). This shows that the actual transition event's time duration is a very small percentage (typically less than 3% in ASICs and other ICs, 10% in ultra high end ICs such as microprocessors) of a clock period. Combining the two statics—that a node transitions in less than 15 clock cycles out of 100 clock cycles (maximum of 15%) and that within the clock cycle that it does transition, the transition current itself flows for less than 10% time of that clock period), it can be concluded that, a node spends almost 98%-99% time waiting to do useful work (a transition activity) while it spends less than 2% time in actually doing useful work (making a transition).
As shown in FIG. 3, a leakage current or static current 204 of the node is always present in all nodes. This is not a new phenomenon. These statistics and electrical behavior (of transition current being there only for a small percentage of time duration while leakage current is always present for any given node) have always been present in all ICs using CMOS technology. However, the leakage current, though always present, has been a very small percentage of the transition current and of the total current until recently. In modern ICs, leakage current is a large percentage of transition and total current. Hence, the need to reduce or eliminate leakage current is more critical with modern ICs than it was in the past.
As mentioned above, dynamic or active power consumption of ICs is proportional to the number of transitions made by all nodes in that IC. When the number of node transitions is less, the chip consumes less dynamic or active power. IC designers use the concept of clock gating, for the less active node in an IC, to force the “clock” to NOT transition. Unfortunately, the leakage or static current still flows through all nodes whether transitioning or not. Therefore, dedicated design efforts need to be invested in reducing or eliminating the leakage or static current (or leakage or static power).
FIG. 4 illustrates general structures of current technologies that are used in the industry for leakage reduction. In these technologies, leakage current reduction is accomplished using a special signal called “Sleep” or “Standby” or something equivalent. This signal may be used in conjunction with low leakage MOS devices (PMOS 122 and NMOS 123 in FIG. 4) in series with the main pull up and pull down paths and in series with the main computation circuit 121 to reduce leakage when the whole functional block may be inactive or less functional and not doing its full useful function. This specially configured sleep signal is generated using a specialized functional block(s) (a sleep monitoring block). The sleep signal represents a time period when a functional unit, many functional unit or the complete chip is guaranteed to be inactive or non-functional. Sleep signals and associated MOS devices need to be generated and designed for each sub-block, block or multiple of BLOCKs that needs to be switched OFF, independently. In these devices, special architectural features are designed to recognize such opportunities and generate these “sleep” or “standby” signals. Such opportunities when one of multiple blocks can be switched OFF simultaneously are difficult to recognize and implement.
As shown in FIG. 4, a footer NMOS transistor 123 and a header PMOS transistor 122 is placed in series with the “Pull down circuit” and “Pull up circuit” respectively. The gate terminals of these footer and header transistors are connected to special “sleep” or “standby” signals from sleep/standby pin(s) 126, 127. For this circuit, the NMOS and PMOS devices 122, 123 used for the footer and header are special “Low Leakage” transistors available from all semiconductor foundries. Once an appropriate logic level is asserted on sleep signals (Logic “HIGH” on “Sleep 1” and Logic “Low” on “Sleep 2”), the footer and header transistors are off and the leakage of this functional block 121 is equal to the leakage of the footer and header devices 122, 123.
However, there are many limitations of the mechanism shown in FIG. 4. For example, the footer and header devices 122, 123 used in series of main functional pull down and pull up paths and the main computation logic block 121 unfortunately slow down the main functionality of the large logic block 121. In particular, since in CMOS circuits, leakage current and speed of operation are proportional to each other so that increasing the speed of the footer and header devices 122, 123 also increases the leakage current thereby mitigating the very effect these technologies are designed to create. Thus, the speed of a circuit that uses the mechanism in FIG. 4 tends to be substantially slower.
Another limitation of the leakage reduction technology in FIG. 4 is that, due to practical limitations, the header and footer devices 122, 123 can only be used with large functional blocks and, in general, the larger the block size, the smaller the probability to find appropriate opportunity to assert the sleep mode on the block. This means that the opportunities to reduce leakage current using these technologies are limited, thus the effect of leakage reduction using such techniques is also limited.
Yet another limitation of the leakage reduction technologies in FIG. 4 is that the designer must design special functional blocks to generate the “Sleep” signals. These blocks are tedious to design and require changes in the architecture of the IC which in turn affects the software and programming of the chip. Change in software requires changes in complete eco-system in the manufacturing process and usage of the IC. It is undesirable for any IC to need modifications in its usage environment because it may limit the marketability of the IC itself. In addition, architectural changes in an IC also requires new functional verification efforts for the IC that are very expensive. For these reasons IC design teams attempt to limit or eliminate changes that would require architectural (hence software) modification. This limitation further reduces the probability of finding opportunities when a big functional block can be in “sleep” or “standby” mode.
FIG. 5 show that a functional unit or chip (IC) is in sleep mode (162) in between active mode (161) in time. To reduce leakage using “sleep” or “standby” signal, one need to maximize time interval represented by “sleep” mode 161. However, as explained above, doing so is a difficult, costly and inefficient task. As shown, the opportunities to put a block in sleep mode are small which means small leakage current reductions. This figure represents statistical behavior of functional blocks (that it is difficult to find opportunities to put a block in standby or sleep mode). This also makes sense from design philosophy point of view. A functional-block in an IC is designed and implemented to do useful work, not to be idle. If a functional block is idle most of the time, then the block design and usage is inefficient, which in general is against design and implementation methodologies used in industry because such inefficiency result in expensive ICs that are commercially not very successful.
FIG. 6 illustrates a device that uses sleep signals “SBB” and “SB” with a chain of inverters 141. These are sleep signal for this structure. These sleep signals cause virtual supply rails 146, 147, 149 and 150 to be disconnected from the static (and actual IC) supply rails 148 and 151. This disconnection causes virtual supplies and hence sources of inverters connected to the appropriate supplies to drift to a different voltage than the static supply rails 148 and 151. This causes a negative gate biasing voltage to the MOS transistors that are supposed to be “OFF” and the leakage reduction in OFF transistors due to negative gate biasing is substantial. However, the technique shown in FIG. 4 can be used only with a chain of inverters (not in a single inverter and not with general logic functions) and hence is not useful of majority of functional and circuit blocks in an IC. Moreover, the voltages on virtual supply nodes are non-deterministic which means that charge on nodes in a block is not guaranteed to be retained when this structure goes in “sleep” or “standby” mode. To mitigate the problem, the system may have a memory structure placed at important/relevant/all nodes so that the logic is deterministic in sleep or standby mode. The requirement of a memory bit for all important or relevant nodes or all nodes is too much overhead. The active power increase of three extra structures is likely to be more than the saving realized in reduction of leakage current. Also this technology is applicable only for a chain of inverters which represents an insignificant percentage of logic functionality (if at all) within any IC. Virtual voltage being non-deterministic presents a reliability issue that needs to be mitigated with elaborate circuit structures otherwise the logic block driven by this structure may malfunction. This means that this technology is not implementable in practical commercial ICs.
It is desirable to provide a reduced leakage current semiconductor device and method of manufacture that reduces leakage current when the device is not transitioning which occurs more than 95% of the time and it is to this end that the disclosure is directed.